Throughout September we managed to pay money for some Haswell-EP samples for a fast run by way of our testing suite. The Xeon E5 v3 vary extends past that of the E5 v2 with the brand new structure, help for DDR4 and extra SKUs with extra cores. These are usually cut up into a number of markets together with workstation, server, low energy and excessive efficiency, with a couple of SKUs devoted for communications or off-map SKUs with totally different ranges of help. Immediately we’re testing two 10 core fashions, the Xeon E5-2687W v3 and the Xeon E5-2650 v3.
Intel Xeon E5 v3: The Info
Our preliminary Haswell-EP protection from Johan was tremendous in depth and nicely value a learn for anybody within the Xeon platform. My focus right here will probably be mild as compared, mentioning key factors that as an ex-workstation consumer I discover fascinating. This would be the first of a number of critiques on the Xeon processors, which we now have cut up as much as focus extra on every space.
The core layouts for every of the totally different ranges of processor are from three designs, emulating the only and twin ring bus sort preparations relying on the variety of cores in every SKU. As with the Xeon E5 v2 processors, the large block of cache is in the midst of the cores and knowledge is transferred by way of the ring bus. From the core designs, pairs of cores may be disabled to make decrease core rely CPUs, and very similar to the earlier era, some low core / excessive cache fashions is perhaps attainable.
Within the 10-12 core picture above we primarily get two courses of cores – one within the massive stack to the left and one other to the best. The processor is designed to deal with all cores equally, though the Cluster on Die snoop mode new to E5 v3 will manage the cache knowledge into what acts like two huge sections in a NUMA fashion-association. This enables knowledge related to cores that want it to remain shut and hopefully scale back learn/write latencies, however is all clear to the consumer. Johan goes into extra element on this entrance in his evaluate.
This column association can also be why we don’t see the progressive leap in cores we might anticipate. Within the shopper area, we now have had 1, 2, four, 6, eight cores, and one may anticipate 12 and sixteen on the horizon, however 10, 14 and 18 appear somewhat off canter, alongside witht the 15-core design from Ivy Bridge-EP. Utilizing this column design, Intel has to stability the variety of cores per ring and the variety of cores per column. Within the giant 18 core design there are 10 cores within the secondary ring and six in a single column – ideally fewer columns can be preferable nevertheless extra rings permits knowledge to switch extra steadily. It turns into a little bit of a stability in terms of design, effectivity, efficiency and yield on the finish of the day, particularly when dealing with as much as 5.69B transistors in 662 mm2.
Intel must be providing sure configurations with extra L3 cache, provided that of their press supplies the one they labelled ’10C-12C’ will truly be provided as a minimize down to 6 cores for launch. These CPUs, whichever means you slice them, are nonetheless large.
Immediately our evaluate revolves round two of the 10 core choices from Intel.
The E5-2687W v3 is an fascinating mannequin of the bunch, notably because of the significance of the E5-2687W v2 from the earlier era. The v2 model was lauded because of the distinction in peak frequencies in comparison with the upper core rely fashions, however this modifications with Haswell-EP.
For Ivy Bridge-EP:
– The eight-core E5-2687W v2 gave three.6 GHz in full-load, TDP of 150W for $2108,
– The 12 core E5-2697 v2 gave three.zero GHz in full-load, TDP of 130W for $2614
– The 10-core E5-2687W v3 provides three.2 GHz for 160W at $2057,
– The 14-core E5-2697 v3 provides three.1 GHz for 145W at $2702 or
– The 18-core E5-2699 v3 provides 2.eight GHz for 145W at $4115
If we examine the distinction between the E5-2687W and E5-2697, first with v2 and then v3, it makes the brand new Haswell ‘W for Workstation’ CPU rather less engaging. Beforehand it was a commerce-off between cores and frequency, and relying on the software program having a excessive turbo mode helps with the v2 CPUs.
To make issues worse for the E5-2687W v3, if we examine single thread speeds, the E5-2697 v3 reaches three.6 GHz in comparison with the E5-2687W v3 at three.5 GHz, which places the W processor at an obstacle.
It’s value noting that Intel places these two processors in several elements of the product stack, to technically they shouldn’t be ‘competing’ towards one another:
The E5-2687W v3 is firmly for Workstations solely, quite than servers, whereas the E5-2697 v3 ought to find yourself in 2U servers.
The opposite processor on this assessment, the E5-2650 v3 sits within the ‘Superior’ part within the SKU stack, giving 2.6 GHz at load or three.zero GHz for single threaded velocity, however lists at solely 105W for $1166 tray worth.
Utilizing this info and a number of SKUs which are off-roadmap, the turbo modes of the 10 core processors are:
All of the 10 core processors attain their full-core turbo when 5 cores are in use, and are on the highest turbo frequency when one or two cores are lively.
Once we reviewed a pair of the E5 v2 processors again in March, the primary server based mostly chipsets on the time revolved across the C600 collection, codename ‘Patsburg’. For the v3 processors, this strikes to the C610 collection, also called Wellsburg. The C612 chipset is the first server element at this level, providing most of the options we have now already seen in our X99 critiques:
– As much as 10 SATA 6 Gbps,
– 6 ports of USB three.zero,
– eight ports of USB 2.zero
– As much as eight PCIe 2.zero, with x1/x2/x4 supported
New options for C610 collection embrace:
– Lowered TDP, Common Energy and Package deal (now 7W, 25mm x 25mm)
– Intel SVT
– USB three.zero XHCI Debug
– Help for MCTP Protocol and Finish Factors
– Help for Administration Visitors over DMI
– SPI Enhancements
Intel vPro, SPS three.zero, RSTe and CAS are additionally supported.
For the SATA/USB3/PCIe bencwidth mixtures, Intel has carried out an prolonged from of Flex IO. It virtually seems to be a lot the identical at Z87 and Z97, providing 22 quite than 18 differential sign pairs. A specific amount of those pairs are fastened to USB3 / PCIe / SATA however two pairs are muxed:
This slide exhibits 18 sign pairs, though I discussed 22. It’s because the final 4 are from a secondary AHCI controller giving 4 extra SATA 6 Gbps ports. Like X99, the draw back of those secondary SATA ports is that they don’t seem to be RAID succesful as a result of limitations inside the silicon.
MTCP over PCIe can also be an fascinating new addition to Wellsburg, permitting cross CPU communication from controllers hooked up to the opposite aspect of the system:
We nonetheless have a shopper class DDR4 assessment within the works, however the improve from DDR3 to DDR4 for Haswell-EP is extra vital. The lower in energy consumption is usually listed is the simplest-to-clarify profit, giving an approximate 2W saving at-the-wall per reminiscence module:
One necessary facet of DDR4 would be the greater reminiscence frequency, particularly when extra DIMMs per channel are put in. It may additionally come to move that some server motherboard producers will find yourself supporting the DDR4-2133 at 3DPC, just like some efforts made with Patsburg.
In a variety of Intel supplies we acquired, it was value noting that non-ECC UDIMM help just isn’t typically listed with the brand new Haswell-EP CPUs, however we will affirm that in our testing, all of our CPUs labored with commonplace shopper grade UDIMMs.
December 16, 2014
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December 12, 2014